Typically, an electronic apparatus is provided with a logic circuit that performs signal processing and a PLL circuit that generates a clock signal used by the logic circuit to perform operations. FIG. 1 is an electric block diagram illustrating a configuration example of a conventional PLL circuit 50.
The PLL circuit 50 includes a PLL part 51 and a crystal oscillator circuit 52. In the PLL circuit 50, a reference signal Sr generated by the crystal oscillator circuit 52 is converted by the PLL part 51 into a clock signal Clk having a preset frequency (target frequency), and the clock signal Clk is output to an internal circuit (not illustrated).
The PLL part 51 includes first and second frequency dividers 55 and 56, a phase comparator 57, a charge pump 58, a loop filter 59, and a voltage controlled oscillator (VCO) 60 serving as a clock oscillator.
A clock signal Clk output from the VCO 60 is input to the first frequency divider 55. The first frequency divider 55 performs frequency dividing on the clock signal Clk input at a preset division ratio and outputs the signal as a feedback clock signal Sp to the phase comparator 57.
That is, the first frequency divider 55 receives the clock signal Clk to be output to a logic circuit as an external circuit (not illustrated) in order to perform feedback control, performs frequency dividing on the received clock signal Clk, and outputs the signal to the phase comparator 57.
A reference signal Sr output from the crystal oscillator circuit 52 is an input to the second frequency divider 56. The second frequency divider 56 performs frequency dividing on the reference signal Sr input at a preset division ratio and outputs the signal as a frequency-divided reference signal Srd to the phase comparator 57.
The feedback clock signal Sp output from the first frequency divider 55 and the frequency-divided reference signal Srd output from the second frequency divider 56 are input to the phase comparator 57. The phase comparator 57 compares the phase of the feedback clock signal Sp input with the phase of the frequency-divided reference signal Srd input, thereby detecting a phase difference therebetween, and outputs an up signal Sup and a down signal Sdo having a pulse width according to the phase difference to the charge pump 58. Here, the up signal Sup causes the charge pump 58 in the subsequent stage to output an H-level judgment signal Sj, whereas the down signal Sdo causes the charge pump 58 in the subsequent stage to output an L-level judgment signal Sj.
That is, when the frequency of the feedback clock signal Sp is equal to the frequency of the frequency-divided reference signal Srd, no phase difference occurs between the feedback clock signal Sp and the frequency-divided reference signal Srd. At this time, the phase comparator 57 outputs neither an up signal Sup nor a down signal Sdo. That is, when there is no phase difference between the feedback clock signal Sp and the frequency-divided reference signal Srd, the clock signal Clk has the preset frequency (target frequency). Therefore, the phase comparator 57 outputs neither an up signal Sup nor a down signal Sdo.
When the frequency of the feedback clock signal Sp is lower than the frequency of the frequency-divided reference signal Srd, a phase difference occurs between the feedback clock signal Sp and the frequency-divided reference signal Srd. At this time, the phase comparator 57 outputs an up signal Sup having a pulse width according to the phase difference.
That is, in the phase comparator 57, as the frequency of the feedback clock signal Sp is lower than the frequency of the frequency-divided reference signal Srd, the phase difference between the feedback clock signal Sp and the frequency-divided reference signal Srd is larger. At this time, the phase comparator 57 outputs an up signal Sup having a large pulse width according to the phase difference.
On the other hand, in the phase comparator 57, when the frequency of the feedback clock signal Sp is lower than the frequency of the frequency-divided reference signal Srd and as the frequencies of the both signals Sp and Srd are more approximate to each other, the phase difference between the feedback clock signal Sp and the frequency-divided reference signal Srd is smaller. At this time, the phase comparator 57 outputs an up signal Sup having a small pulse width according to the phase difference.
When the frequency of the feedback clock signal Sp is higher than the frequency of the frequency-divided reference signal Srd, a phase difference occurs between the feedback clock signal Sp and the frequency-divided reference signal Srd. At this time, the phase comparator 57 outputs a down signal Sdo having a pulse width according to the phase difference.
That is, in the phase comparator 57, as the frequency of the feedback clock signal Sp is higher than the frequency of the frequency-divided reference signal Srd, the phase difference between the feedback clock signal Sp and the frequency-divided reference signal Srd is larger. At this time, the phase comparator 57 outputs a down signal Sdo having a large pulse width according to the phase difference.
On the other hand, in the phase comparator 57, when the frequency of the feedback clock signal Sp is higher than the frequency of the frequency-divided reference signal Srd and as the frequencies of the both signals Sp and Srd are more approximate to each other, the phase difference between the feedback clock signal Sp and the frequency-divided reference signal Srd is smaller. At this time, the phase comparator 57 outputs a down signal Sdo having a small pulse width according to the phase difference.
In this way, the phase comparator 57 outputs an up signal Sup and/or a down signal Sdo for causing the feedback clock signal Sp to be approximate to the frequency-divided reference signal Srd, and operates to cause the frequency of the clock signal Clk to be approximate to the preset frequency (target frequency).
The up signal Sup and the down signal Sdo output from the phase comparator 57 are input to the charge pump 58. The charge pump 58 outputs a judgment signal Sj to the loop filter 59 on the basis of the up signal Sup and the down signal Sdo input thereto. Specifically, when the up signal Sup is input, the charge pump 58 outputs an H-level judgment signal Sj. On the other hand, when the down signal Sdo is input, the charge pump 58 outputs an L-level judgment signal Sj.
Therefore, when the frequency of the clock signal Clk is lower than the preset frequency (target frequency), the charge pump 58 outputs an H-level judgment signal Sj. On the other hand, when the frequency of the clock signal Clk is equal to or higher than the present frequency (target frequency), the charge pump 58 outputs an L-level judgment signal Sj.
The judgment signal Sj output from the charge pump 58 is input to the loop filter 59. The loop filter 59 smoothes the judgment signal Sj input and outputs the signal as a control signal Slf to the VCO 60. When the L-level judgment signal Sj is output for a longer time than the time the H-level judgment signal Sj is output, the loop filter 59 decreases the voltage level of the control signal Slf. On the other hand, when the L-level judgment signal Sj is output for a shorter time than the time the H-level judgment signal Sj is output, the loop filter 59 increases the voltage level of the control signal Slf.
That is, when the frequency of the clock signal Clk is lower than the preset frequency (target frequency), the charge pump 58 increases the voltage level of the control signal Slf. On the other hand, when the frequency of the clock signal Clk is equal to or higher than the target frequency, the charge pump 58 decreases the voltage level of the control signal Slf.
The control signal Slf output from the loop filter 59 is input to the VCO 60. The VCO 60 changes the frequency of the clock signal Clk in accordance with the voltage level of the control signal Slf input thereto and outputs the clock signal Clk to the internal circuit and the first frequency divider 55. That is, the VCO 60 increases the frequency of the clock signal Clk, as the voltage level of the control signal Slf is higher, and outputs the clock signal Clk. Meanwhile, the VCO 60 decreases the frequency of the clock signal Clk, as the voltage level of the control signal Slf is lower, and outputs the clock signal Clk.
That is, the PLL part 51 repeats the above-described operation, causing the frequency of the clock signal Clk to match (e.g. be locked to) the preset frequency (target frequency). As illustrated in FIG. 2, the crystal oscillator circuit 52 includes a crystal oscillator 65, a feedback resistor 66, an inverting amplifier circuit 67 formed of a CMOS (Complementary Metal-Oxide Semiconductor) transistor, and a buffer circuit 68. The crystal oscillator 65 and the feedback resistor 66 are connected in parallel. Among nodes between the crystal oscillator 65 and the feedback resistor 66 (nodes N10 and N11), the node N10 is connected to an output terminal of the inverting amplifier circuit 67 and an input terminal of the buffer circuit 68, whereas the node N11 is connected to an input terminal of the inverting amplifier circuit 67.
With this configuration, in the crystal oscillator circuit 52, the inverting amplifier circuit 67 amplifies a sinusoidal signal output from the crystal oscillator 65 and outputs the signal as an amplified signal Sa to the buffer circuit 68. Accordingly, the crystal oscillator circuit 52 outputs the input amplified signal Sa as the reference signal Sr to the PLL part 51 via the buffer circuit 68.
In the crystal oscillator circuit 52, noise of a voltage level, according to a drive capability of the inverting amplifier circuit 67, is mixed in the reference signal Sr. Specifically, in the crystal oscillator circuit 52, noise in the reference signal Sr becomes larger as the drive capability of the inverting amplifier circuit 67 is higher. On the other hand, in the crystal oscillator circuit 52, noise in the reference signal Sr becomes smaller as the drive capability of the inverting amplifier circuit 67 is lower. Therefore, the PLL circuit 50 has a problem of generating a clock signal Clk on the basis of a reference signal Sr with noise, resulting in a poor jitter characteristic of the clock signal Clk due to fluctuations in a time axis direction at rising and falling edges of the clock signal Clk. Also, the PLL circuit 50 causes noise in a power supply as the drive capability is higher, causing a negative influence on other circuits, and causing a poor jitter characteristic of the clock signal Clk.
As a result, in order to improve the jitter characteristic of the clock signal Clk, it may be necessary to decrease the drive capability of the inverting amplifier circuit 67 of the crystal oscillator circuit 52 so as to reduce the noise in the reference signal Sr input from the crystal oscillator circuit 52. However, when the drive capability of the inverting amplifier circuit 67 of the crystal oscillator circuit 52 is decreased, crystal oscillation does not start, or time is taken to amplify a sinusoidal signal output from the crystal oscillator 65 of the crystal oscillator circuit 52. That is, no sinusoidal signal is output from the crystal oscillator 65, or it takes time to cause the sinusoidal signal output from the crystal oscillator 65 to have a voltage level necessary for a logic operation of the buffer circuit 68. For this reason, in the PLL circuit 50, the time when the frequency of the clock signal Clk does not match the preset frequency (target frequency) or the time for realizing match (lock) with the target frequency (lockup time) is long.
Under such circumstances, in the conventional crystal oscillator circuit 52, the drive capability of the inverting amplifier circuit 67 is switched, at startup, when the crystal oscillator circuit 52 is being started and, in a normal state, when the crystal oscillator circuit 52 is outputting a reference signal Sr of a constant frequency. That is, in the crystal oscillator circuit 52, the drive capability of the inverting amplifier circuit 67 is equal to a conventional drive capability at startup, whereas the drive capability of the inverting amplifier circuit 67 is lower than the conventional drive capability in the normal state (e.g., Japanese Unexamined Patent Application Publication No. 11-308103).
In other words, at startup, the drive capability of the inverting amplifier circuit 67 of the crystal oscillator circuit 52 is equal to the conventional drive capability, so that the lockup time for causing the frequency of the clock signal Clk to match the preset frequency (target frequency) is substantially similar to in the conventional case in the PLL circuit 50. On the other hand, in a normal state, the drive capability of the inverting amplifier circuit 67 of the crystal oscillator circuit 52 is lower than the conventional drive capability, so that the jitter characteristic of the clock signal Clk is improved in the PLL circuit 50.
FIG. 3 is a voltage waveform diagram of an amplified signal Sa output from the inverting amplifier circuit 67 of the crystal oscillator circuit 52. When the drive capability of the inverting amplifier circuit 67 is high (at startup), the amplified signal Sa output from the inverting amplifier circuit 67 rises and falls quickly, as in a waveform 70 illustrated in FIG. 3. On the other hand, when the drive capability of the inverting amplifier circuit 67 is low (in a normal state), the amplified signal Sa rises and falls slowly, as in a waveform 71 illustrated in FIG. 3. Then, when the amplified signal Sa is input to the buffer circuit 68, a large phase difference occurs between when the drive capability of the inverting amplifier circuit 67 is high (at startup) and when the drive capability is low (in a normal state). For example, assume that a threshold voltage of the buffer circuit 68 is half of a power-supply voltage Vcc, then a difference of time tb occurs between cases where the drive capability of the inverting amplifier circuit 67 is high and low.
That is, in the voltage level of the amplified signal Sa output from the inverting amplifier circuit 67 of the crystal oscillator circuit 52, the rise time and fall time thereof change in accordance with the drive capability of the inverting amplifier circuit 67 of the crystal oscillator circuit 52.
When the drive capability of the inverting amplifier circuit 67 of the crystal oscillator circuit 52 is switched at startup and in a normal state of the PLL circuit 50, the phase significantly changes, and thus the frequency of the clock signal Clk significantly departs from the frequency before the switch of the drive capability. As such, time is taken to recover the frequency before the switch of the drive capability, so that the PLL circuit 50 is incapable of stably outputting the clock signal Clk.